Senior ASIC Digital Design Lead for High-Speed Optics

Cisco Systems, Inc; Allentown (Lehigh County); On-site; USD 178,000 - 257,000; Full time

Benefits offered by this job

401(k) with company match

Paid parental leave

Disability insurance

Life insurance

Paid time off

Job summary

Cisco Systems, Inc. is seeking a Digital Design Technical Leader for Silicon One Optics. You will architect digital blocks and lead cross-functional teams across digital, analog, firmware and physical design to deliver next-gen 100G/200G/400G silicon.

Own the full ASIC lifecycle from concept through tapeout and post-silicon validation, defining architectures and integrating advanced SerDes/IP, while driving power/performance optimization for a high-performance computing backbone.

Qualifications

• Bachelors + 12 years of related experience, or Masters + 8 years, or PhD + 5 years.
• Digital design experience with FSMs, CPU subsystems, complex SoCs, and FPGA validation.
• Experience managing full ASIC/SoC design flow.
• Experience with key bus protocols and high-speed SerDes, Ethernet, and/or D2D IP.

Responsibilities

• Define digital architectures for next-gen optics and 100G/200G/400G interconnects.
• Lead cross-functional teams across digital, analog, firmware and physical design.
• Own full ASIC lifecycle from concept to tapeout to post-silicon production.
• Drive technical strategy and integrate cutting-edge IPs.
• Improve power and performance while maintaining design quality.

Skills

Digital design

FSMs & CPU subsystems

ASIC/SoC design flow

High-speed SerDes/IP

Education

Bachelor's degree in EE/CS (or related)

Master's degree (EE/CS)

PhD (optional)

Tools

SPI/I2C/AXI

Ethernet/IP

Job description

Cisco Systems, Inc. is seeking a Digital Design Technical Leader for Silicon One Optics. You will architect digital blocks and lead cross-functional teams across digital, analog, firmware and physical design to deliver next-gen 100G/200G/400G silicon.

Own the full ASIC lifecycle from concept through tapeout and post-silicon validation, defining architectures and integrating advanced SerDes/IP, while driving power/performance optimization for a high-performance computing backbone.