Lead ASIC DFT & Test Architect

Cisco Systems, Inc; San Jose (CA); On-site; USD 187,000 - 308,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Bonus opportunities

Job summary

Cisco Systems, Inc. is seeking a senior ASIC design engineer to join the Silicon One team in the United States.

You will collaborate with Front-end RTL and backend physical design teams to drive high-quality test, IP development, and chip integration, ensuring robust silicon solutions that meet Cisco’s standards for performance and innovation. The role requires 10+ years in ASIC design, strong Verilog/SystemVerilog skills, and experience with front-end tools and protocol interfaces.

Qualifications

• 10+ years of ASIC digital design experience.
• Proficiency in Verilog/SystemVerilog coding.
• Experience with front-end tools (simulators, linting, CDC checkers, synthesis, formal verification).
• Familiarity with AMBA protocols and JTAG; memory interfaces.

Responsibilities

• Drive high-quality Structural test, functional test and diagnostic feature implementation.
• Develop IP and integration work, including test access with high-speed IO and protocols.
• Collaborate with Front-end RTL and backend physical design teams on chip architecture.
• Ensure silicon solutions meet Cisco's performance and innovation standards.

Skills

ASIC design

RTL knowledge

Tools

Verilog/SystemVerilog

Verilog simulators

linting

CDC checkers

synthesis

formal verification

AMBA protocols (AXI/APB/AHB)

JTAG

memories

Job description

Cisco Systems, Inc. is seeking a senior ASIC design engineer to join the Silicon One team in the United States.

You will collaborate with Front-end RTL and backend physical design teams to drive high-quality test, IP development, and chip integration, ensuring robust silicon solutions that meet Cisco’s standards for performance and innovation. The role requires 10+ years in ASIC design, strong Verilog/SystemVerilog skills, and experience with front-end tools and protocol interfaces.