Senior ASIC Physical Design Architect (Fullchip)

Cisco Systems; San Jose (CA); On-site; USD 251,000 - 363,000; Full time

Job summary

Cisco Systems in San Jose is seeking an experienced ASIC/Fullchip engineer to lead complex floorplanning and migration efforts for cutting‑edge silicon platforms. You will work with RTL, design, and EDA teams to craft robust, low‑power, high‑performance implementations.

The role emphasizes hierarchical design, timing closure, and advanced clock/mesh techniques, with opportunities to leverage Python and AI tools to improve productivity and outcomes.

Qualifications

• Bachelor’s degree in Engineering with significant ASIC experience required.
• Experience with RTL2GDSII flow and multiple tapeouts in advanced nodes.

Responsibilities

• Fullchip floorplanning with architecture understanding and IP constraints.
• Collaborate with RTL, EDA vendors, and design teams to integrate requirements into floorplan.
• Perform hierarchical implementation including partitioning, clock plan, and pad/bump planning.
• RTL-to-GDSII flow covering floorplan, power grid, place and route, STA, and physical verification.

Skills

RTL2GDSII flow

Fullchip floorplan

Hierarchical design

Timing closure

Static timing analysis

Python

AI tools usage

Education

Bachelor’s degree in Engineering

Master’s degree in Engineering

PhD in Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems in San Jose is seeking an experienced ASIC/Fullchip engineer to lead complex floorplanning and migration efforts for cutting‑edge silicon platforms. You will work with RTL, design, and EDA teams to craft robust, low‑power, high‑performance implementations.

The role emphasizes hierarchical design, timing closure, and advanced clock/mesh techniques, with opportunities to leverage Python and AI tools to improve productivity and outcomes.