Senior ASIC RTL Engineer — DFT & Verification Lead

Cisco Systems, Inc; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking a senior RTL/Silicon design engineer focused on Design for Test (DFT) RTL. You will collaborate with front-end RTL and backend physical design teams to ensure robust silicon architectures for Cisco’s Silicon One family.

You will drive high-quality DFT RTL across chip architecture, working to meet performance and innovation standards while integrating with Verilog/SystemVerilog design flows and AMBA interfaces.

Qualifications

• Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
• Proficiency in Verilog/SystemVerilog coding.
• Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Experience with AMBA interfaces (AXI, APB, AHB) and memories.

Responsibilities

• Drive high-quality Design for Test RTL to ensure robust silicon.
• Collaborate with RTL and physical design teams to understand chip architecture.
• Deliver silicon solutions meeting Cisco standards for performance and innovation.

Skills

Verilog/SystemVerilog coding

SystemVerilog

AMBA protocols

JTAG

Synthesis

Formal verification

Linting

CDC checks

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Tools

Verilog simulators

Linting tools

CDC checkers

Synthesis tools

Formal verification tools

Job description

Cisco Systems, Inc. is seeking a senior RTL/Silicon design engineer focused on Design for Test (DFT) RTL. You will collaborate with front-end RTL and backend physical design teams to ensure robust silicon architectures for Cisco’s Silicon One family.

You will drive high-quality DFT RTL across chip architecture, working to meet performance and innovation standards while integrating with Verilog/SystemVerilog design flows and AMBA interfaces.