Senior ASIC Design Engineer - High-Performance RTL

Cisco Systems, Inc; San Jose (CA); Sur place; USD 168 000 - 245 000; Plein temps

Résumé du poste

Cisco Systems, Inc. is seeking an experienced ASIC design engineer to take end-to-end Front-End ownership of ASIC subsystems for Cisco platforms.

You will work with a multi-disciplinary team to meet stringent power, performance and area goals, contributing to process improvements and reusable design techniques. You will design high-frequency RTL in Verilog/SystemVerilog, lead reviews, mentor teammates, and collaborate with verification and physical design to ensure robust silicon and timely

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering with ASIC design experience.
• Experience delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced tech nodes.
• High-performance RTL design using Verilog/SystemVerilog.
• Understanding of timing closure, power optimization, and clock gating techniques.
• Experience with ASIC development flows including simulation, synthesis, and static timing analysis.

Responsabilités

• Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in Cisco platforms.
• Contribute to a multi-disciplined engineering team to meet power, performance, and area goals for products.
• Help define the process, methods, and tools for design and implementation of complex developments.
• Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
• Design and implement high-frequency, high-performance RTL in Verilog / SystemVerilog, meeting aggressive timing, power, and area targets.
• Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
• Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
• Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
• Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
• Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
• Creates re-usable code that promotes efficiencies in new ways
• Influence system architecture and key design decisions across complex ASIC subsystems.

Connaissances

Verilog

SystemVerilog

Timing closure

Power optimization

Clock gating

ASIC development flows

Simulation

Synthesis

Static timing analysis

Formation

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

Description du poste

Cisco Systems, Inc. is seeking an experienced ASIC design engineer to take end-to-end Front-End ownership of ASIC subsystems for Cisco platforms.

You will work with a multi-disciplinary team to meet stringent power, performance and area goals, contributing to process improvements and reusable design techniques. You will design high-frequency RTL in Verilog/SystemVerilog, lead reviews, mentor teammates, and collaborate with verification and physical design to ensure robust silicon and timely