Senior DFT Engineer (Remote) - Lead ASIC Test & IJTAG

Encore Semi, Inc.; Dallas (TX); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

15 days PTO per year

10 paid holidays per year

Comprehensive medical benefits (80% of

premiums for employee and dependents

Dental & Vision: 50% premiums

Life Insurance, FSA, HAS & GAP

Employee Assistance Program (EAP)

401k Traditional & Roth

Job summary

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs in a fully remote US role. You will drive DFT requirements from RTL to silicon bring-up, ensuring top-notch test coverage and robust fault analysis.

The ideal candidate brings 8+ years of ASIC DFT experience, IJTAG expertise, and strong proficiency with Tessent tools, Verilog/SystemVerilog, and scripting. This position offers salary, benefits, and bonuses for a remote US-based candidate.

Qualifications

• 8+ years of proven industry experience in ASIC DFT engineering.
• Strong hands-on expertise with IEEE 1687 (IJTAG) architecture, including ICL and PDL formats.
• Deep proficiency with the Mentor Graphics Tessent tool suite.
• Solid simulation/verification skills with Xcelium, VCS, or QuestaSim.
• Fluency in Verilog/SystemVerilog and strong scripting abilities (Tcl, Python, or Perl).

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

ASIC DFT engineering

IJTAG architecture

Verilog/SystemVerilog

Scripting: Tcl/Python/Perl

RTL-to-silicon DFT integration

Education

BS or MS in Electrical/Computer Engineering

Tools

Mentor Tessent

Job description

Encore Semi, Inc. is seeking a Senior DFT Engineer to lead test architecture for complex SoCs in a fully remote US role. You will drive DFT requirements from RTL to silicon bring-up, ensuring top-notch test coverage and robust fault analysis.

The ideal candidate brings 8+ years of ASIC DFT experience, IJTAG expertise, and strong proficiency with Tessent tools, Verilog/SystemVerilog, and scripting. This position offers salary, benefits, and bonuses for a remote US-based candidate.