Senior DFT Engineer for AI Silicon

Unconventional AI; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals

Job summary

Unconventional AI is redefining AI hardware by mapping neural networks to device physics for extreme efficiency. We seek a foundational Member of Technical Staff, DFT Engineer, to lead test architectures spanning 2.5D/3D packaging and analog macro testability.

You will influence architecture, testability, and yield on cutting-edge silicon. The role emphasizes cross-disciplinary collaboration, innovative DFT methodologies, and influencing micro-architecture for power, performance, and area.

Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years in digital DFT and test architecture; tapeouts on 7nm/5nm or newer preferred.
• Technical Expertise: scan compression, MBIST, fault modeling, ATPG.
• Physical design challenges in advanced nodes and impact on test reliability.
• STA and timing closure for complex designs in shift and capture test modes.
• Design Flow Proficiency: mastery of standard EDA CAD tool suites; scripting in Tcl/Python/Perl.
• Communication: excellent written and verbal; experience managing external vendors.

Responsibilities

• Lead DFT Architecture & Implementation using CAD tools for scan compression, MBIST, and JTAG.
• Drive bottom-up hierarchical DFT methodologies for large-scale SoCs.
• Own DFT strategy with foundry interfaces to improve yield for test chips.
• Advance Multi-Stacked Die DFT for 2.5D/3D packaging; ensure coverage across interfaces.
• Develop test strategies for Analog Macro DFT integration.
• Drive test coverage, test time, and yield targets with Architects for better PPA.
• Own final DFT sign-off including ATPG, fault validation, and STA timing closure.
• Contribute to design flow automation and best practices for testability.
• Evaluate potential partners offering AI tools to improve chip design.

Skills

Digital DFT & test architecture

Tapeouts (7nm/5nm)

Scan compression

MBIST generation

Fault modeling

ATPG

Physical design challenges

STA & timing closure

EDA CAD tools

Scripting: Tcl/Python/Perl

Communication

Advanced Packaging Test

Custom AI Hardware

Mixed-Signal Integration

AI Tools

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Job description

Unconventional AI is redefining AI hardware by mapping neural networks to device physics for extreme efficiency. We seek a foundational Member of Technical Staff, DFT Engineer, to lead test architectures spanning 2.5D/3D packaging and analog macro testability.

You will influence architecture, testability, and yield on cutting-edge silicon. The role emphasizes cross-disciplinary collaboration, innovative DFT methodologies, and influencing micro-architecture for power, performance, and area.