Neuromorphic SoC DFX/DFT Lead for AI Hardware

Intel Corporation; Folsom (CA); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel's Neuromorphic Computing Lab in Oregon is seeking a senior product development engineer to shape DFT/DFX for the Loihi neuromorphic silicon program. You will define test methodologies, enable high-volume production, and collaborate with design architects to push asynchronous circuits beyond traditional AI constraints.

You will lead test strategy, fault coverage, power-on testing, and tool flows across SoC levels, while partnering with circuit experts to create robust manufacturing

Qualifications

• Must have hands-on DFT experience from architecture to silicon bring-up.
• Architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
• Ownership of IP and SoC-level scan constructs (e.g., boundary scan, TAP, BIST/MBIST).
• Experience debugging post-silicon and driving circuit changes for testability and reliability improvements.

Responsibilities

• Architect a complete DFT solution at the SoC level, including synchronous and asynchronous designs.
• Lead scan-insertion and compression flow-development at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models for test vector generation and pre-silicon validation.
• Collaborate with designers to drive DFT/DFD/DFM features for manufacturing readiness (HVM).
• Lead silicon power-on, enable tester content, debug failures, and maintain tooling.

Skills

DFT stack architecture

IP ownership (IP/SoC)

Post-silicon debugging

Asynchronous design

AI tool flows

Education

Bachelor's degree + 6+ years DFT

Master's degree + 4+ years DFT

Job description

Intel's Neuromorphic Computing Lab in Oregon is seeking a senior product development engineer to shape DFT/DFX for the Loihi neuromorphic silicon program. You will define test methodologies, enable high-volume production, and collaborate with design architects to push asynchronous circuits beyond traditional AI constraints.

You will lead test strategy, fault coverage, power-on testing, and tool flows across SoC levels, while partnering with circuit experts to create robust manufacturing