AI Silicon, DFT Engineer

Unconventional AI; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

401k matching

Unlimited PTO

Complimentary meals

Job summary

Unconventional AI is redefining AI hardware by mapping neural networks to device physics for extreme efficiency. We seek a foundational Member of Technical Staff, DFT Engineer, to lead test architectures spanning 2.5D/3D packaging and analog macro testability.

You will influence architecture, testability, and yield on cutting-edge silicon. The role emphasizes cross-disciplinary collaboration, innovative DFT methodologies, and influencing micro-architecture for power, performance, and area.

Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years in digital DFT and test architecture; tapeouts on 7nm/5nm or newer preferred.
• Technical Expertise: scan compression, MBIST, fault modeling, ATPG.
• Physical design challenges in advanced nodes and impact on test reliability.
• STA and timing closure for complex designs in shift and capture test modes.
• Design Flow Proficiency: mastery of standard EDA CAD tool suites; scripting in Tcl/Python/Perl.
• Communication: excellent written and verbal; experience managing external vendors.

Responsibilities

• Lead DFT Architecture & Implementation using CAD tools for scan compression, MBIST, and JTAG.
• Drive bottom-up hierarchical DFT methodologies for large-scale SoCs.
• Own DFT strategy with foundry interfaces to improve yield for test chips.
• Advance Multi-Stacked Die DFT for 2.5D/3D packaging; ensure coverage across interfaces.
• Develop test strategies for Analog Macro DFT integration.
• Drive test coverage, test time, and yield targets with Architects for better PPA.
• Own final DFT sign-off including ATPG, fault validation, and STA timing closure.
• Contribute to design flow automation and best practices for testability.
• Evaluate potential partners offering AI tools to improve chip design.

Skills

Digital DFT & test architecture

Tapeouts (7nm/5nm)

Scan compression

MBIST generation

Fault modeling

ATPG

Physical design challenges

STA & timing closure

EDA CAD tools

Scripting: Tcl/Python/Perl

Communication

Advanced Packaging Test

Custom AI Hardware

Mixed-Signal Integration

AI Tools

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Job description

About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

The Role

As a Member of Technical Staff, DFT Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the testability realization of our novel computing platform, ensuring that our complex digital logic and custom mixed-signal blocks can be reliably tested.

Responsibilities

• DFT Architecture & Implementation: Lead the implementation of comprehensive test architectures using industry-standard CAD tools. This includes the insertion, configuration, and verification of scan compression, Memory Built-In Self-Test (MBIST), and JTAG/boundary scan logic.


• Hierarchical DFT Implementation: Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs, managing core-level test wrapping, pattern retargeting, and top-level test integration to optimize runtime and capacity limits.


• Foundry Interface & Defect Analysis: Own the overarching DFT strategy, working closely with foundry interfaces to analyze defect densities and drive yield improvements for test chips.


• Multi-Stacked Die DFT: Drive cutting-edge DFT methodologies for 2.5D/3D multi-stacked die packaging. You will ensure comprehensive test coverage across die-to-die interfaces utilizing emerging standards like IEEE 1838.


• Analog Macro DFT: Work at the interface of digital and analog design to facilitate the integration and testability of custom analog mixed-signal blocks. You will develop novel test strategies for non-standard analog macros operating within the digital fabric.


• Test & PPA Optimization: Drive aggressive test coverage, test time, and yield targets while working closely with architects to influence the micro-architecture for better Power, Performance, and Area (PPA).


• Sign-off & Verification: Own the final DFT sign-off process. This includes Automatic Test Pattern Generation (ATPG), test vector validation, fault simulation, and ensuring clean timing closure during Static Timing Analysis (STA) for all test modes.


• Methodology Development: Contribute to the development and automation of our design flow. Set best practices for testability to ensure first-pass silicon success.


• Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency.

Minimum Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.


• Experience: 10+ years of industry experience in digital DFT and test architecture, with a track record of successful tapeouts on modern process nodes (7nm, 5nm, or newer preferred).


• Technical Expertise:




• Deep expertise in scan compression, MBIST generation, fault modeling (stuck-at, transition, path delay), and ATPG.


• Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation) and their impact on test reliability.


• Expertise in Static Timing Analysis (STA) and timing closure for complex designs in shift and capture test modes.




• Design Flow Proficiency:




• Expert-level mastery of standard EDA CAD tool suites for DFT implementation and vector generation.


• Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.




• Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.

Preferred Qualifications (Nice To Have)

• Advanced Packaging Test: Hands-on experience with modern die-to-die (D2D) interconnect test strategies, chiplet testing, and 3D-IC DFT architectures.


• Custom AI Hardware: Experience with test architecture for Machine Learning accelerators or large-scale systolic arrays.


• Mixed-Signal Integration: Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.


• AI Tools: Familiarity with state of the art AI tools to accelerate chip design.

Why Join Us?

• The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.


• The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.


• The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.


• The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Mountain View office.