Remote DFT Architect for AI Chiplet/SOC

TYLsemi; San Jose (CA); Remote; USD 238,000 - 286,000; Full time

Job summary

TylSemi, Inc. seeks an experienced DFT Architect to lead the Design-for-Test strategy for complex ASIC/SOC designs.

You will define end-to-end DFT architecture, including scan with compression, MBIST, boundary scan, SSN, and at-speed testing, partnering with RTL, PD, and verification. You will drive test coverage, silicon bring-up, yield analysis, and automation, mentor junior engineers, and deliver robust DFT solutions that scale with advanced nodes.

Qualifications

• 10+ years of ASIC/SOC DFT implementation and architecture.
• Expert in scan, ATPG, MBIST, JTAG, compression, and low-power DFT.
• Hands-on with Tessent, DFT Compiler/TestMAX, or equivalents.
• Strong RTL design, timing, physical design constraints, silicon debug understanding.
• Experience with advanced technology nodes and large SOC integration.
• Strong scripting and automation using Tcl, Python, Perl, or Shell.
• Excellent leadership, problem-solving, and cross-functional collaboration skills.

Responsibilities

• Define and own SOC-level DFT architecture and test strategy.
• Lead implementation of scan insertion, ATPG, MBIST, boundary scan, SSN implementation, and test compression methodologies.
• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
• Analyze and resolve DFT-related timing, routing, and testability challenges.
• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.
• Mentor junior engineers and provide technical leadership across projects.

Skills

DFT architecture

ATPG

MBIST

JTAG

Scan compression

RTL timing

Silicon debugging

Automation scripting

Leadership

Cross-functional

Education

Bachelors or Masters in Electronics/Electrical/VLSI

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

Job description

TylSemi, Inc. seeks an experienced DFT Architect to lead the Design-for-Test strategy for complex ASIC/SOC designs.

You will define end-to-end DFT architecture, including scan with compression, MBIST, boundary scan, SSN, and at-speed testing, partnering with RTL, PD, and verification. You will drive test coverage, silicon bring-up, yield analysis, and automation, mentor junior engineers, and deliver robust DFT solutions that scale with advanced nodes.