Lead DFT Architect for Next-Gen AI Chips

SambaNova; San Jose (CA); Sur place; USD 180 000 - 255 000; Plein temps

Avantages offerts par ce poste

Equity

Medical insurance

HSA

Well-being benefits

Résumé du poste

SambaNova Systems is seeking a Principal Design for Test (DFT) Engineer to help build state-of-the-art RDU chips for ML/AI. You will own DFT architecture, verification, ATPG, MBIST and silicon bring-up for high-performance chips.

Responsibilities include defining DFT for large SoCs, maintaining ATPG flows, automating DFT tasks, and integrating JTAG/IJTAG interfaces for test access. Collaboration with STA and PD teams is required to meet timing closure and yield goals.

Qualifications

• BS in CS/CE or related field; 10+ years experience.
• Deep knowledge of scan insertion, ATPG, MBIST, JTAG.
• STA constraints and DFT timing experience preferred.

Responsabilités

• Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs.
• Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
• Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
• Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
• Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
• Work closely with STA and Physical Design teams on DFT timing closure.
• Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Connaissances

DFT architecture

ATPG

MBIST

JTAG

Verilog/System-Verilog

Formation

B.S. in CS/CE or related

Outils

Siemens Tessent

Description du poste

SambaNova Systems is seeking a Principal Design for Test (DFT) Engineer to help build state-of-the-art RDU chips for ML/AI. You will own DFT architecture, verification, ATPG, MBIST and silicon bring-up for high-performance chips.

Responsibilities include defining DFT for large SoCs, maintaining ATPG flows, automating DFT tasks, and integrating JTAG/IJTAG interfaces for test access. Collaboration with STA and PD teams is required to meet timing closure and yield goals.