New Grad DFT Engineer - AI Hardware R&D

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a highly motivated DFT Engineer to join our hardware team in Santa Clara. You will own end-to-end DFT for the world’s most sophisticated chips, from methodology through post‑silicon support.

Collaborate with top EDA vendors, drive capabilities to NVIDIA requirements, and partner with VLSI and Operations teams to deploy scan features across product lines. Mentoring junior engineers on test designs is also expected.

Qualifications

• Pursuing a MS or PhD (or equivalent experience).
• Define scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation.
• Good exposure to RTL, clocks design, STA, place‑n‑route and power trade‑offs.
• Experience in silicon debug and bring‑up on the ATE with understanding of pattern formats, failure processing, and test program development.

Responsibilities

• In this highly technical role, you will work on end-to-end DFT for the most sophisticated chips in the world, from methodology, to deployment to post‑silicon lifecycle support.
• Partner with the top EDA tool vendors to develop new capabilities to support NVIDIA requirements, and with internal CAD to drive efficiency via automations.
• Work with NVIDIA VLSI and Operations teams to deliver the scan feature in all product segments at NVIDIA.
• Help mentor junior engineers on test designs and trade‑offs including cost and quality.

Skills

DFT concepts

Perl scripting

Python scripting

Tcl scripting

RTL/VHDL

Education

MS or PhD in related field

Tools

ATP/ATPG tools

Fault simulation tools

Pattern formats

Job description

NVIDIA is seeking a highly motivated DFT Engineer to join our hardware team in Santa Clara. You will own end-to-end DFT for the world’s most sophisticated chips, from methodology through post‑silicon support.

Collaborate with top EDA vendors, drive capabilities to NVIDIA requirements, and partner with VLSI and Operations teams to deploy scan features across product lines. Mentoring junior engineers on test designs is also expected.