Lead DFT Engineer for Self-Improving AI Chips

Ricursive Intelligence; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Ricursive Intelligence is seeking a DFT engineer to own end-to-end testability for complex SoCs at advanced nodes. You will architect and insert DFT, plan MBIST, analyze fault models, and sign off ATPG patterns from pre-silicon to tapeout, while collaborating with RTL, DV, and physical design teams.

You will also drive post-silicon bring-up with foundry and OSAT partners and shape AI-enabled DFT tools. You will work in a small, fast-paced team, defining foundational DFT methodology and

Qualifications

• BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.
• 5+ years of hands-on DFT experience owning the full lifecycle on complex SoCs or IPs: DFT architecture and specification, scan and compression insertion, MBIST and BISR, boundary scan and IJTAG, test-mode timing constraints, DFT verification and DRC closure, fault-model and coverage analysis, and ATPG pattern generation and signoff.
• Day-one fluency in at least one production DFT stack and gate-level simulation, with strong Tcl and Python scripting and enough Verilog/SystemVerilog to write and debug test logic and testbenches yourself.
• Post-silicon experience on silicon that taped out and shipped to production: converted and brought up ATPG and MBIST patterns on ATE, debugged CP, FT, and SLT failures, and worked directly with foundry and OSAT partners.
• Practical, demonstrated use of AI coding and agentic tools in your own engineering work, with clear ideas about where they help in a DFT flow and where they do not.

Responsibilities

• Own DFT architecture and insertion for complex silicon at advanced nodes: hierarchical scan and compression, BIST, MBIST and BISR planning and repair, boundary scan, and IJTAG networks (IEEE 1149.1, etc), integrated with the synthesis, physical design, and STA flow from RTL to GDS.
• Define the fault-model and coverage strategy (stuck-at, transition, path-delay, cell-aware, and bridging) and own ATPG generation, fault simulation, coverage closure, pattern verification in zero-delay and SDF gate-level simulation, and DFT signoff to tapeout, making explicit tradeoffs between coverage, test time, pattern count, and area.
• Drive post-silicon test from first silicon to production: ATE pattern conversion and bring-up, CP (wafer sort), FT, and SLT program development and debug, scan diagnosis and failure analysis, and yield and DPPM improvement, working hands-on with our foundry and OSAT partners.
• Integrate DFT with RTL, DV, and physical design: set DFT requirements at the micro-architecture stage, verify test logic alongside functional verification, close test-mode timing with the PD and STA engineers, and take on RTL design and DV work directly when the program needs it.
• Make DFT AI-native: shape how AI plans, closes and debugs DFT, measured in coverage, test time and DPPM.
• Partner cross-functionally on chip design infrastructure and automation, encoding DFT knowledge as reusable flows, checks, and evaluation targets that the rest of the team and our AI systems can build on.

Skills

DFT architecture

MBIST

ATPG signoff

boundary scan

fault-model analysis

coverage analysis

Verilog/SystemVerilog

Tcl scripting

Python scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field

Tools

Verilog/SystemVerilog

Tcl scripting

Python scripting

Job description

Ricursive Intelligence is seeking a DFT engineer to own end-to-end testability for complex SoCs at advanced nodes. You will architect and insert DFT, plan MBIST, analyze fault models, and sign off ATPG patterns from pre-silicon to tapeout, while collaborating with RTL, DV, and physical design teams.

You will also drive post-silicon bring-up with foundry and OSAT partners and shape AI-enabled DFT tools. You will work in a small, fast-paced team, defining foundational DFT methodology and