Senior DFT Engineer: ASIC Test & Silicon Bring-Up

Normal Computing Corporation; Mountain View (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own DFT architecture for next-generation ASICs, driving scan/ATPG, MBIST, and boundary-scan strategies from RTL through tapeout and silicon bring-up.

You will collaborate with RTL, verification, physical design, and silicon product engineering teams, establishing scalable DFT flows and partnering with external partners to deliver production-ready test patterns and collateral. Strong leadership and scripting skills are essential.

Qualifications

• 7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
• Strong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
• Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
• Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
• Strong scripting skills in Python, Tcl, or similar languages.
• Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams.

Responsibilities

• DFT Architecture: Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
• Implementation & Integration: Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.
• Test Coverage & Signoff: Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.
• Manufacturing Test Readiness: Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns and test collateral to our manufacturing partners, and documentation for ATE integration, silicon bring-up, and diagnosis.
• Methodology & Tooling: Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools, supporting future ASIC programs.
• External Partner Collaboration: Define technical requirements, oversee contracted DFT work, and review deliverables to ensure quality and integration with Normal’s silicon development process.

Skills

DFT architecture

ATPG

MBIST

boundary scan/JTAG

test pattern generation

RTL/verification/physical design

Python/Tcl scripting

cross-functional collaboration

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own DFT architecture for next-generation ASICs, driving scan/ATPG, MBIST, and boundary-scan strategies from RTL through tapeout and silicon bring-up.

You will collaborate with RTL, verification, physical design, and silicon product engineering teams, establishing scalable DFT flows and partnering with external partners to deliver production-ready test patterns and collateral. Strong leadership and scripting skills are essential.