Senior DFT Architect for SoCs & AI-Driven Test

Voltai; Palo Alto (CA); In loco; USD 140.000 - 200.000; Tempo pieno

Descrizione del lavoro

Voltai is seeking a senior DFT architect to ensure testability of SoCs and IPs across manufacturing and the field. You will own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.

You will drive architecture, implement patterns, and collaborate with RTL, synthesis, and physical design teams to optimize test coverage, yield, and time-to-market.

Competenze

• 5+ years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Tcl and Python scripting.

Mansioni

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
• Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

Conoscenze

DFT architecture

ATPG

Tcl scripting

Python scripting

MBIST

IEEE 1149.1/1687

Strumenti

Tessent

TestMAX

Modus

Descrizione del lavoro

Voltai is seeking a senior DFT architect to ensure testability of SoCs and IPs across manufacturing and the field. You will own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.

You will drive architecture, implement patterns, and collaborate with RTL, synthesis, and physical design teams to optimize test coverage, yield, and time-to-market.