Lead DFT Architect for Next‑Gen AI Compute ASIC

Neurophos; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health coverage

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Personalized benefits

Job summary

Neurophos is hiring a DFT Architect to own design-for-test across our ASICs. You will define the DFT strategy, sign off coverage, and collaborate with RTL and physical design teams to integrate testability from the start.

This is the first dedicated DFT hire, enabling growth of the test team and alignment with analog test needs. You will work with the analog team on their test requirements and shepherd handoff to post-silicon testing, ensuring robust test coverage and scalable test flows for

Qualifications

• 8 to 15 years in DFT, with hands-on ownership of scan, ATPG, and MBIST.
• Architect-level experience on a large digital ASIC: assess full chip, set DFT strategy, own coverage signoff.
• Experience developing and specifying functional test vectors to augment structural coverage.
• Track record through tapeout on a complex compute ASIC.

Responsibilities

• Own DFT architecture and test control design for multiple ASIC devices using ATPG, scan, MBIST and JTAG.
• Architect on-die memory test, including controller specification and generation, pattern selection and system test time/power analysis.
• Collaborate with operations/PE teams to ensure all test modes are implemented, including HAST.
• Develop system-level DFT plans for all product phases and sign off coverage.

Skills

DFT expertise

ATPG & MBIST

Chip-level signoff

Tapeout experience

Tools

Cadence tooling

Silicon photonics test

Job description

Neurophos is hiring a DFT Architect to own design-for-test across our ASICs. You will define the DFT strategy, sign off coverage, and collaborate with RTL and physical design teams to integrate testability from the start.

This is the first dedicated DFT hire, enabling growth of the test team and alignment with analog test needs. You will work with the analog team on their test requirements and shepherd handoff to post-silicon testing, ensuring robust test coverage and scalable test flows for