Senior DFT Architect for Space ASICs

United States Digital Space LLC; Palo Alto (CA); On-site; USD 220,000 - 355,000; Full time

Benefits offered by this job

Stock options

Employee Stock Purchase Plan

Medical, vision, dental

401(k)

Disability Insurance

Life Insurance

Paid parental leave

Vacation (3 weeks)

Paid holidays (10+)

Paid sick leave

Discretionary bonuses

Discounts

Job summary

United States Digital Space LLC is seeking a Principal DFT Engineer (Silicon Engineering) in Palo Alto to lead advanced DFT architectures for space and ground infrastructure. You will drive scan insertion, ATPG, and post-silicon validation while coordinating RTL and physical design DRC checks with cross-disciplinary teams.

You will also develop automated test scripts using Perl, Python, Tcl, or C+, and work with Siemens Tessent and UPF to ensure robust fault models and test coverage.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 10+ years of experience working with ASICs.
• 10+ years of experience in scan insertion and DFT setup, integration and validation.

Responsibilities

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non-timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

Skills

Leadership experience

RTL experience

Clock domain crossings

Power optimization

Formal verification

DFT rule checking

ATE testers

Education

Bachelor’s degree in electrical/computer engineering or computer science

Tools

Verilog/SystemVerilog

UPF

Siemens Tessent

DRC tooling

Job description

United States Digital Space LLC is seeking a Principal DFT Engineer (Silicon Engineering) in Palo Alto to lead advanced DFT architectures for space and ground infrastructure. You will drive scan insertion, ATPG, and post-silicon validation while coordinating RTL and physical design DRC checks with cross-disciplinary teams.

You will also develop automated test scripts using Perl, Python, Tcl, or C+, and work with Siemens Tessent and UPF to ensure robust fault models and test coverage.