Senior ASIC DFT Engineer for Space-Grade SoCs

United States Digital Space LLC; Austin (CA); On-site; USD 165,000 - 260,000; Full time

Benefits offered by this job

Stock options

401(k)

Medical, vision, dental

Paid parental leave

Disability insurance

3 weeks vacation

Job summary

United States Digital Space LLC is seeking a Sr. ASIC DFT Engineer (Silicon Engineering) to develop and optimize DFT architectures for space-grade ASICs, leveraging Tessent tools and industry standards.

You will collaborate with cross-disciplinary teams to implement, verify, and characterize DFT features across complex SoCs/ASICs. The role emphasizes post-silicon bringup, IST/boundary scan, ATPG pattern generation, and scripting in Python/C++.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or physics.
• 5+ years of experience in semiconductor DFT engineering, post-silicon validation, and/or production testing.
• Master's or PhD in electrical engineering, computer engineering, physics, or related field.
• Extensive post-silicon bringup experience including silicon debug, failure analysis, and yield optimization on complex SoCs/ASICs.
• Experience with Automated Test Equipment (ATE) platforms for high-volume manufacturing test development and debug.
• Knowledge of industry standards for testability (IEEE 1500, 1687) and low-power DFT techniques using Siemens Tessent.
• Experience with IST, boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools.
• Hands-on experience with Tessent Streaming Scan Network.
• Experience with cell-aware fault models in ATPG.

Responsibilities

• Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools.
• Integration and verification of DFT IPs and fabrics within Subsystems.
• Set up and run ATPG tools and methodologies, including patterns for stuck-at, transition, and path delay fault models with pattern compression and hierarchical flows.
• Run and debug non-timing and SDF annotated gate-level simulations.
• Create and validate DFT patterns for post-silicon bringup and assist ATE debugging through silicon characterization cycles.
• Develop test scripts and automate processes using Perl, Python, Tcl, or C++.

Skills

DFT engineering

Post-silicon bringup

Tessent tools

ATPG

Boundary scan

Python

C++

SoC/ASIC

Debugging

Education

BS in Electrical/CS/Physics

MS/PhD in EE/CE/Physics

Tools

Siemens Tessent

Teradyne

Advantest

IST

Tessent Streaming Scan Network

IEEE 1500/1687

Job description

United States Digital Space LLC is seeking a Sr. ASIC DFT Engineer (Silicon Engineering) to develop and optimize DFT architectures for space-grade ASICs, leveraging Tessent tools and industry standards.

You will collaborate with cross-disciplinary teams to implement, verify, and characterize DFT features across complex SoCs/ASICs. The role emphasizes post-silicon bringup, IST/boundary scan, ATPG pattern generation, and scripting in Python/C++.