Senior DFT Architect for High-Performance SoCs

QFocus Technologies; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA, is seeking a Senior DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs, collaborating with front-end, physical design, verification and product teams.

You will lead pre-silicon activities, implement DFT architectures (Scan, ATPG, MBIST, JTAG), and drive post-silicon bring-up and yield improvements in a fast-paced environment.

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development.

Responsibilities

• Pre-Silicon Execution: Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Pre-Silicon Execution: Perform Scan Chain Insertion, stitching, and optimization for timing closure and power grid compatibility.
• Pre-Silicon Execution: Integrate MBIST controllers, repair mechanisms, and memory test routines.
• Pre-Silicon Execution: Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Pre-Silicon Execution: Execute Verilog/SystemVerilog simulations for gate-level DFT validation with SDF.
• Pre-Silicon Execution: Run DFT linting with SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Post-Silicon Production & Bring-up: Translate ATPG/MBIST patterns into tester formats (WGL, STIL) for ATE deployment.
• Post-Silicon Production & Bring-up: Support post-silicon bring-up, debugging first-silicon DFT features, and pattern conversion.
• Collaborate with Product and Test Engineering teams to optimize test time and boost manufacturing yield.

Skills

Verilog / SystemVerilog

Scan Insertion

ATPG

MBIST

JTAG

Post-Silicon Support

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

QFocus Technologies in Sunnyvale, CA, is seeking a Senior DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs, collaborating with front-end, physical design, verification and product teams.

You will lead pre-silicon activities, implement DFT architectures (Scan, ATPG, MBIST, JTAG), and drive post-silicon bring-up and yield improvements in a fast-paced environment.