Senior DFT Architect – Silicon ASICs

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 220,000 - 355,000; Full time

Benefits offered by this job

Stock options

401(k)

Paid parental leave

Healthcare benefits

Job summary

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead DFT architecture design for next-generation ASICs used in Starlink and space systems. You will collaborate with cross-disciplinary teams across systems, firmware, design, validation, and ASIC implementation to push silicon capabilities and reliability.

Responsibilities include ATPG pattern generation, RTL/DRC readiness checks, DFT fabrics integration, and non-timing/SDF simulations.

Qualifications

• Bachelor’s degree in EE/CE/CS.
• 10+ years of experience with ASICs.
• 10+ years of experience in scan insertion and DFT

Responsibilities

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non-timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

Skills

DFT concepts

ATPG

Verilog/SystemVerilog

RTL debugging

Python/Perl

Education

Bachelor’s degree in EE/CE/CS

Tools

Siemens Tessent

UPF

SDF

Job description

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead DFT architecture design for next-generation ASICs used in Starlink and space systems. You will collaborate with cross-disciplinary teams across systems, firmware, design, validation, and ASIC implementation to push silicon capabilities and reliability.

Responsibilities include ATPG pattern generation, RTL/DRC readiness checks, DFT fabrics integration, and non-timing/SDF simulations.