Senior DFT Architect for Space ASICs

Future Ventures; Palo Alto (CA); On-site; USD 220,000 - 355,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision & dental coverage

Paid time off – 3 weeks

10+ paid holidays

Job summary

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead the design‑for‑test efforts for Starlink ASICs. You will drive DFT architecture, scan insertion, memory and logic‑BIST, and work with RTL, gate netlists, and Siemens Tessent tools across cross‑functional teams.

The role emphasizes ATPG pattern generation, post‑silicon validation, UPF, Verilog/SystemVerilog proficiency, and test automation using Python/Tcl. SpaceX offers competitive compensation and extensive benefits.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering or computer science.
• 10+ years of experience with ASICs.
• 10+ years of experience in scan insertion and DFT setup, integration and validation.

Responsibilities

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation.
• Own ATPG tools and methodologies, including generating patterns for stuck‑at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post‑silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non‑timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

Skills

DFT architectures

ATPG tools

RTL debugging

Verilog/SystemVerilog

UPF

Python scripting

DFT/Integration

Design for Test

Education

Bachelor's degree in electrical engineering, computer engineering or computer science

Tools

Siemens Tessent

RTL/physical DRC tools

Job description

SpaceX is seeking a Principal DFT Engineer (Silicon Engineering) to lead the design‑for‑test efforts for Starlink ASICs. You will drive DFT architecture, scan insertion, memory and logic‑BIST, and work with RTL, gate netlists, and Siemens Tessent tools across cross‑functional teams.

The role emphasizes ATPG pattern generation, post‑silicon validation, UPF, Verilog/SystemVerilog proficiency, and test automation using Python/Tcl. SpaceX offers competitive compensation and extensive benefits.