Senior DFT Architect for AI ASICs

Etched.ai; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving med

Housing subsidy of $2k per month

Relocation support for San Jose (Sant—

Wellness benefits

Daily lunch + dinner in office

Job summary

Etched.ai, based in San Jose, CA, seeks a seasoned DFT Engineer to ensure robust testability of ICs from design to production. You will implement DFT architectures, integrate scan, BIST, MBIST, and drive improvements in coverage, yield, and reliability.

The role emphasizes collaboration with design, verification, and test teams. The ideal candidate has 10+ years in DFT, strong SystemVerilog skills, and hands-on experience with leading EDA tools, along with scripting expertise to streamline

Qualifications

• 10+ years of experience in DFT engineering for ASIC/SoC products.
• Deep understanding of digital design, verification methodologies, and DFT implementation practices.
• Proficiency in SystemVerilog and fluency with industry-standard EDA tools (Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
• Scripting/automation experience using Python, Perl, or TCL to streamline DFT.
• Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon.
• Strong analytical and debugging skills across teams.
• Excellent communication and collaboration abilities.

Responsibilities

• Develop and implement robust DFT architectures for ASIC/SoC designs to enhance test coverage and fault isolation.
• Integrate scan insertion, boundary scan, BIST, MBIST into designs.
• Collaborate with design and verification teams to address DFT requirements early.
• Analyze test results and silicon debug data to improve coverage, yield, and reliability.
• Create and execute DFT verification plans for all DFT features.
• Apply simulation-based and formal verification techniques for DFT correctness.
• Conduct internal DFT audits and design reviews to identify gaps.
• Support silicon bring-up, debug, and failure analysis post-silicon.
• Partner with test engineering to develop Automated Test Equipment (ATE) for volume production.
• Generate production-quality test patterns and robust failure analysis capabilities.
• Collaborate with manufacturing and quality teams for data-driven test improvements.

Skills

SystemVerilog

EDA tools

Automation scripting

Debugging

Cross-functional collaboration

Communication

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s preferred

Tools

Synopsys DFT Compiler

Cadence Encounter Test

Mentor Tessent

Job description

Etched.ai, based in San Jose, CA, seeks a seasoned DFT Engineer to ensure robust testability of ICs from design to production. You will implement DFT architectures, integrate scan, BIST, MBIST, and drive improvements in coverage, yield, and reliability.

The role emphasizes collaboration with design, verification, and test teams. The ideal candidate has 10+ years in DFT, strong SystemVerilog skills, and hands-on experience with leading EDA tools, along with scripting expertise to streamline