Senior DFT Engineer for SoCs & AI-Driven Testing

Voltai; United States; On-site; USD 140,000 - 230,000; Full time

Job summary

Voltai is seeking a seasoned DFT engineer to ensure our chips test cleanly in manufacturing and in the field. You will own DFT architecture on real silicon programs with leading semiconductor partners while helping Voltai's AI learn DFT methodologies.

You will collaborate with RTL, synthesis, and physical design teams, define scan and MBIST strategies, insert and verify DFT logic, and build automation to report coverage and improve yield.

Qualifications

• 5+ years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Tcl and Python scripting.

Responsibilities

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
• Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

Skills

DFT experience

Gate-level simulation

Tcl scripting

Python scripting

Tools

Tessent

TestMAX

Modus

Job description

Voltai is seeking a seasoned DFT engineer to ensure our chips test cleanly in manufacturing and in the field. You will own DFT architecture on real silicon programs with leading semiconductor partners while helping Voltai's AI learn DFT methodologies.

You will collaborate with RTL, synthesis, and physical design teams, define scan and MBIST strategies, insert and verify DFT logic, and build automation to report coverage and improve yield.