ASIC DFT Engineer

Cisco Systems, Inc.; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Cisco Systems, Inc. is seeking an ASIC Implementation Engineer in San Jose, CA. This role focuses on Design-for-Test for next-generation networking chips, requiring 4+ years of relevant experience. Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering and expertise in Jtag protocols, BIST architectures, and DFT tools. Strong debugging skills and the ability to work collaboratively are essential. This position involves influencing design processes and ensuring quality throughout the implementation flow.

Qualifications

• 4+ years experience in ASIC Design for Test.
• Experience with Jtag protocols and BIST architectures.
• Skills in System Verilog Logic Equivalency checking.
• Debugging experience with VCS and other simulators.
• Post-silicon validation using DFT patterns.

Responsibilities

• Implement Hardware Design-for-Test features supporting ATE.
• Develop innovative DFT IP in collaboration with multi-functional teams.
• Participate in creating Hardware DFT & physical design aspects.
• Craft and debug with minimal mentorship.

Skills

ASIC Design for Test Hardware Engineering

Jtag protocols

Scan and BIST architectures

ATPG tools

Verilog design

Scripting skills: Tcl, Python/Perl

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

Job description

Who You'll Work With

You will be in the Silicon One development organization as an ASIC Implementation Engineer in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

What You'll Do

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re‑usable test and debug strategies.
• The job requires the candidate to have the ability to craft and debug with minimal mentorship.

Who You Are

You are an ASIC Design for Test Hardware Engineer with 4+ years of related work experience with a broad mix of technologies including:

Minimum Requirements

• A Bachelor's or Master's Degree, in Electrical or Computer Engineering required with at least 10 years of good experience of latest innovative trends in DFT, test and silicon engineering.
• Good experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Good experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
• Experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Strong verbal skills and ability to thrive in a multifaceted environment
• Scripting skills: Tcl, Python/Perl.

Preferred Skills

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development - Test Architecture, Methodology and Infrastructure
• Test Static Timing Analysis
• Post silicon validation using DFT patterns.