Senior DFT Architect for High-Performance ASICs (Equity)

EF; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Equity & Ownership

Proximity Bonus

Retirement Benefits

Job summary

OLIX seeks Senior/Staff DFT Engineers to own end-to-end DFT for high-throughput ASICs, from test strategy to silicon bring-up. You will drive Scan/ATPG, Boundary Scan, and Memory BIST, ensuring high test coverage and robust fault detection in a fast-paced, cross-disciplinary team.

You will collaborate with RTL, test, and firmware teams to optimize DFT interfaces and test modes, mentor engineers, and push reliable, high-coverage architectures for AI hardware.

Qualifications

• 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs.

Responsibilities

• Architect, own, and implement the comprehensive DFT strategy for complex high-throughput digital pipelines in advanced CMOS nodes.
• Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST.
• Partner with test engineering to develop, validate, and optimize ATE-compatible test patterns to maximise manufacturing yield.
• Drive RTL development with a focus on DFT architecture, including synthesis constraints for test structures.
• Analyse and minimise the DFT impact on power, performance, and area (PPA).
• Collaborate with mixed-signal and software teams to define DFT interfaces and firmware abstractions for test control.
• Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies.

Skills

DFT architecture

Scan/ATPG

Boundary Scan

Memory BIST/Repair

JTAG

Python/Tcl scripting

Verilog/SystemVerilog

PPA optimization

Tools

EDA flows

Pattern simulation

Job description

OLIX seeks Senior/Staff DFT Engineers to own end-to-end DFT for high-throughput ASICs, from test strategy to silicon bring-up. You will drive Scan/ATPG, Boundary Scan, and Memory BIST, ensuring high test coverage and robust fault detection in a fast-paced, cross-disciplinary team.

You will collaborate with RTL, test, and firmware teams to optimize DFT interfaces and test modes, mentor engineers, and push reliable, high-coverage architectures for AI hardware.