Senior DFT Architect for High-Performance ASICs (Equity)

OLIX; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity & ownership

Proximity bonus

Retirement benefits

Job summary

OLIX in Austin, TX is seeking a Senior/Staff DFT Engineer to own end-to-end design-for-test for high‑performance ASICs. You will define test strategies, implement DFT features, and bring up silicon in collaboration with cross‑functional teams.

The ideal candidate has 7+ years in DFT, with experience in Scan/ATPG, Boundary Scan, Memory BIST, and RTL development (SystemVerilog/Verilog/VHDL). Strong scripting in Python or Tcl and a proven ability to improve test coverage and yield.

Qualifications

• 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs.
• Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) on multi‑hundred‑MHz to multi‑GHz clock domains.
• Expertise with industry-standard EDA flows: Scan insertion, ATPG, pattern simulation, fault modeling, and diagnosis tools.
• Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring‑up.
• Strong communication and cross‑functional collaboration abilities in fast-moving environments.

Responsibilities

• Architect, own, and implement the comprehensive DFT strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.
• Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.
• Partner with the test engineering team to develop, validate, and optimize ATE‑compatible test patterns to maximise fault coverage and manufacturing yield.
• Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained‑random verification of DFT logic.
• Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution.
• Collaborate with mixed‑signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis.
• Mentor junior engineers, lead DFT design reviews, and champion best‑practice methodologies for testability and debug across the ASIC development lifecycle.

Skills

DFT architecture

ASIC/SoC verification

RTL design (SystemVerilog/Verilog/VHDL

Python/Tcl scripting

Testability and debug leadership

Cross-functional collaboration

Tools

Scan insertion

ATPG

Boundary Scan

Memory BIST/Repair

Pattern generation tools

Diagnosis tools

Job description

OLIX in Austin, TX is seeking a Senior/Staff DFT Engineer to own end-to-end design-for-test for high‑performance ASICs. You will define test strategies, implement DFT features, and bring up silicon in collaboration with cross‑functional teams.

The ideal candidate has 7+ years in DFT, with experience in Scan/ATPG, Boundary Scan, Memory BIST, and RTL development (SystemVerilog/Verilog/VHDL). Strong scripting in Python or Tcl and a proven ability to improve test coverage and yield.