Senior DFT Lead for ASIC/SoC Testing & Debug

Etched.ai; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Medical Benefits

Housing Subsidy

Relocation Support

Wellness Benefits

Daily Lunch

Unlimited Compute Budget

Job summary

Etched.ai in San Jose, CA seeks a seasoned DFT Engineer to ensure robust testability of ICs from design through production. You will implement DFT architectures, integrate scan, boundary scan, BIST, MBIST, analyze silicon data, and drive test pattern generation for high-volume production.

This role emphasizes collaboration across design, verification, and test teams. You will lead verification plans, apply formal and simulation techniques, and mentor others while staying current with emerging

Qualifications

• 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
• Deep understanding of digital design, verification methodologies, and DFT implementation practices.
• Proficiency in SystemVerilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
• Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.
• Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
• Strong analytical and debugging skills, with ability to work across teams to resolve complex testability issues.
• Excellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).

Responsibilities

• Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
• Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
• Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.
• Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.
• Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.
• Apply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness.
• Conduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage.
• Support silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch.
• Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production.
• Generate production-quality test patterns and ensure robust failure analysis capability in high-volume environments.
• Collaborate with manufacturing and quality teams to implement data-driven test process improvements and monitor long-term product health.
• Ensure test strategies are aligned with product milestones, manufacturing timelines, and quality/reliability targets.
• Author and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides.
• Share best practices through training sessions, onboarding, and mentorship to enhance DFT awareness across design and test teams.
• Stay current with emerging DFT technologies, industry trends, and evolving standards to continually improve internal methodologies.

Skills

DFT engineering

SystemVerilog

Python scripting

Cross-functional leadership

EDA tools

Test pattern generation

Debug & yield analysis

Communication skills

Education

Bachelor's in Electrical/Computer Engineering

Master’s degree preferred

Tools

Synopsys DFT Compiler

Cadence Encounter Test

Mentor Tessent

Job description

Etched.ai in San Jose, CA seeks a seasoned DFT Engineer to ensure robust testability of ICs from design through production. You will implement DFT architectures, integrate scan, boundary scan, BIST, MBIST, analyze silicon data, and drive test pattern generation for high-volume production.

This role emphasizes collaboration across design, verification, and test teams. You will lead verification plans, apply formal and simulation techniques, and mentor others while staying current with emerging