Senior DFT Architect for Next-Gen ASICs

Normal Computing Corp.; Mountain View (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Normal Computing is in search of a seasoned Design-for-Test (DFT) Engineer to own the architecture for our next-generation ASICs, spanning RTL, synthesis, and tapeout. You will lead scan/ATPG, MBIST, boundary-scan, and test-access strategies while collaborating with RTL, verification, physical design, and silicon product engineering teams.

This hands-on leadership role requires establishing scalable DFT flows, guiding external partners, and ensuring manufacturing test readiness from day one.

Qualifications

• 7+ years of experience in DFT implementation for complex ASICs or SoCs.
• Hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
• Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.

Responsibilities

• Own DFT architecture for next-generation ASICs from RTL through tapeout.
• Drive DFT insertion and integration across RTL, synthesis, and physical design.
• Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.
• Partner with manufacturing teams to deliver production-ready test patterns and documentation.

Skills

DFT Architecture

Scan Insertion

ATPG

Scan Compression

MBIST

Boundary Scan/JTAG

DFT Verification

Fault Coverage Analysis

Test Pattern Generation

Scripting (Python/Tcl)

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Normal Computing is in search of a seasoned Design-for-Test (DFT) Engineer to own the architecture for our next-generation ASICs, spanning RTL, synthesis, and tapeout. You will lead scan/ATPG, MBIST, boundary-scan, and test-access strategies while collaborating with RTL, verification, physical design, and silicon product engineering teams.

This hands-on leadership role requires establishing scalable DFT flows, guiding external partners, and ensuring manufacturing test readiness from day one.