Senior DFT Engineer - SoC/ASIC Test Architect

MetAntz; Sunnyvale, Northern (CA, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high‑performance SoCs and ASICs, collaborating with frontend, physical design, verification, and product teams.

You will drive Scan, ATPG, MBIST, and JTAG implementations, translate pre-silicon patterns to tester formats, and support post‑silicon bring‑up to maximize yield. Strong Verilog/SystemVerilog and scripting proficiency required.

Qualifications

• 3+ years hands-on DFT in advanced SoC/ASIC development.
• Strong proficiency in Verilog/SystemVerilog for DFT integration, wrappers, and debugging.
• Experience with scan synthesis, boundary scan, and compressed scan architectures.
• Deep experience generating, debugging, and fault-grading Stuck-at/At-speed patterns.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Perform Scan Chain Insertion, stitching, and optimization for timing closure and power-grid compatibility.
• Integrate MBIST controllers, repair mechanisms, and memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation (SDF).
• Run DFT linting and rule checks using SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Translate pre-silicon ATPG/MBIST patterns into tester formats for ATE deployment.
• Support post-silicon bring-up and yield ramp with pattern conversion and debugging.

Skills

DFT architectures

ATPG patterns

MBIST

JTAG

Scan insertion

Verilog

SystemVerilog

SDF simulation

Scripting (Python/Tcl)

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high‑performance SoCs and ASICs, collaborating with frontend, physical design, verification, and product teams.

You will drive Scan, ATPG, MBIST, and JTAG implementations, translate pre-silicon patterns to tester formats, and support post‑silicon bring‑up to maximize yield. Strong Verilog/SystemVerilog and scripting proficiency required.