Senior DDR/LPDDR Verification Architect

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale, CA seeks a senior ASIC verification engineer to define verification plans for DDR PHY and memory IP blocks. You will design constrained-random SystemVerilog testbenches, write assertions, and close coverage gaps while debugging RTL with design teams.

You will mentor engineers, drive coverage analysis, and integrate AI-assisted tools to improve verification throughput across multiple product generations.

Qualifications

• Bachelor's degree in electrical or computer engineering with 8+ years of ASIC verification experience.
• Deep proficiency in UVM methodology and SystemVerilog for building test benches.
• Strong DDR memory architecture knowledge including timing and calibration flows.

Responsibilities

• Define and track verification test plans for DDR PHY and memory IP blocks translated into executable strategies.
• Design and write constrained-random SystemVerilog testbenches using UVM across product families.
• Write SystemVerilog assertions and functional coverage to close gaps and catch protocol violations.
• Debug RTL and gate-level simulations, root-causing complex memory interface issues with design engineers.
• Perform code coverage analysis and drive closure across verification efforts.
• Mentor junior engineers on test benches, debugging strategies, and verification plans.
• Integrate AI-assisted verification tools and workflows into the verification methodology.

Skills

UVM

SystemVerilog

DDR memory

Memory IP

Debugging

Python/Perl

Scripting

Education

Bachelor's in EE/CE

Tools

Perl

Python

Job description

Synopsys, Inc. in Sunnyvale, CA seeks a senior ASIC verification engineer to define verification plans for DDR PHY and memory IP blocks. You will design constrained-random SystemVerilog testbenches, write assertions, and close coverage gaps while debugging RTL with design teams.

You will mentor engineers, drive coverage analysis, and integrate AI-assisted tools to improve verification throughput across multiple product generations.