Senior Interface IP Verification Lead

Synopsys Inc; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Synopsys Inc is seeking an experienced ASIC Verification Engineer in Austin to own verification of PCIe, CXL, DDR, and Ethernet Interface IP. You will architect and implement scalable UVM environments, define test plans, and drive coverage-driven verification from spec through release.

The role requires 8–10+ years of hands-on verification with SystemVerilog, strong debugging skills, and collaboration with architecture, RTL, firmware, and systems teams.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 8–10+ years of direct ASIC/SoC verification experience.
• Strong SystemVerilog and UVM expertise.
• Proven track record with PCIe, CXL, DDR interfaces and Ethernet.

Responsibilities

• Own verification of complex Interface IP such as PCIe, CXL, DDR, Ethernet.
• Develop and maintain scalable UVM-based verification environments and reusable verification IP.
• Define verification plans and strategies from spec review to product release.
• Create constrained-random, coverage-driven verification solutions using SystemVerilog.
• Drive coverage closure and signoff activities.
• Debug RTL, protocol, and system-level issues; improve automation and efficiency.
• Collaborate with architecture, RTL, firmware, and systems teams; mentor junior engineers.

Skills

SystemVerilog

UVM

PCIe

CXL

DDR

Ethernet

Education

BSEE/B.S. in Electrical Engineering

Tools

VCS

ModelSim

Job description

Synopsys Inc is seeking an experienced ASIC Verification Engineer in Austin to own verification of PCIe, CXL, DDR, and Ethernet Interface IP. You will architect and implement scalable UVM environments, define test plans, and drive coverage-driven verification from spec through release.

The role requires 8–10+ years of hands-on verification with SystemVerilog, strong debugging skills, and collaboration with architecture, RTL, firmware, and systems teams.