Design Verification Engineers DDR

RAPS Consulting Inc; Edison (NJ); Remote; USD 100,000 - 130,000; Full time

Job summary

A leading staffing company is seeking a Design Verification Engineer with over 10 years of experience in ASIC/IP/SoC verification. The role involves defining verification strategies for DDR interfaces and developing testbenches in SystemVerilog. This position offers full-time employment and is remote within the United States. Candidates should have strong technical skills and experience with DDR protocols and simulation tools.

Qualifications

• 10+ years of hands-on experience in ASIC/IP/SoC verification.
• Strong expertise in SystemVerilog, UVM, and functional coverage methodology.
• In-depth understanding of DDR protocols.

Responsibilities

• Define and implement verification strategies and test plans for DDR memory interfaces.
• Develop UVM/SystemVerilog-based testbenches.
• Collaborate with architecture, RTL, and system teams.

Skills

ASIC/IP/SoC verification

SystemVerilog

UVM

DDR3/DDR4/DDR5/LPDDR protocols

Simulation and debug tools

Python scripting

Debugging

Tools

Synopsys VCS

Cadence Xcelium

QuestaSim

Job description

Overview

RAPS Consulting Inc, headquartered in NJ, is one of the nation’s fastest-growing staffing companies. Our mission is to help companies identify the right resources at the right time and cost by building strong relationships with clients and candidates. We specialize in making the best matches through contract, full-time, or payroll services, with a team of qualified and experienced hiring professionals dedicated to this mission.

Position

Design Verification Engineers DDR (either IP or SoC level experience)

Experience – 10+ Years

Location: US Remote

Full Time

Responsibilities

• Define and implement verification strategies and test plans for DDR memory interface designs
• Develop UVM/SystemVerilog-based testbenches and reusable verification components
• Perform protocol-level verification for DDR memory interfaces and validate compliance
• Collaborate with architecture, RTL, and system teams to understand design intent and corner cases
• Own functional coverage, regression setup, and closure
• Integrate DDR models, controllers, PHYs, and validate their interactions
• Debug and resolve simulation failures and functional issues
• Drive code and functional coverage improvements to ensure thorough verification
• Lead or participate in technical reviews and mentor junior engineers

Required Skills

• 10+ years of hands-on experience in ASIC/IP/SoC verification
• Strong expertise in SystemVerilog, UVM, and functional coverage methodology
• In-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocols
• Experience with DDR controllers, PHY integration, and JEDEC standards
• Proficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.
• Good scripting skills in Python, Perl, or Shell for automation and regression management
• Excellent debugging and problem-solving skills
• Familiarity with AXI/AHB protocols and interconnects is a plus
• Experience working with memory models and timing analysis

Preferred Qualifications

• Experience with post-silicon validation or DDR hardware bring-up
• Knowledge of formal verification tools and techniques
• Experience with low power verification and timing closure tools

Job Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Engineering and Information Technology
• Industries: IT Services and IT Consulting