Senior ASIC RTL Design Engineer - LPDDR PHY & Power

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale seeks an experienced ASIC digital design engineer with RTL ownership to deliver production RTL for LPDDR PHY IP across mobile and AI applications.

You will optimize timing, power and area across multiple process nodes, develop Perl automation for design generation, and collaborate with architecture, verification and physical design teams to meet schedule commitments.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of ASIC digital design experience with RTL ownership in production silicon.
• Expert Verilog proficiency for timing-critical designs.
• Strong Perl scripting skills for design automation.
• Deep knowledge of synthesis, timing analysis, and power optimization.

Responsibilities

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation.
• Optimize designs to meet timing, power, and area targets across multiple process nodes.
• Develop Perl automation for design generation and flow integration.
• Collaborate with cross-functional teams to resolve timing and power challenges.
• Contribute to design reviews and methodology development.

Skills

ASIC digital design

RTL ownership

Verilog

Timing analysis

Power optimization

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

Tools

Perl scripting

Job description

Synopsys, Inc. in Sunnyvale seeks an experienced ASIC digital design engineer with RTL ownership to deliver production RTL for LPDDR PHY IP across mobile and AI applications.

You will optimize timing, power and area across multiple process nodes, develop Perl automation for design generation, and collaborate with architecture, verification and physical design teams to meet schedule commitments.