Senior Pre-Silicon IP Verification Engineer

Synopsys Inc; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys Inc. is seeking an experienced ASIC Verification Engineer to own verification of Interface IP.

You will design, develop, and maintain scalable UVM-based environments for PCIe, CXL, DDR, and Ethernet, collaborating with architects, RTL, and firmware teams to ensure high-quality, robust silicon products. The role emphasizes coverage-driven verification, debugging, and early issue detection, contributing to the reliability and performance of AI accelerators, data centers, and networking

Qualifications

• Minimum 5 years of verification experience on ASIC/SoC design.
• Deep SystemVerilog/UVM expertise and industry-standard simulators.
• Strong knowledge of PCIe, CXL, DDR, Ethernet protocols.

Responsibilities

• Own verification of complex Interface IP solutions, including PCIe, CXL, DDR, and Ethernet technologies.
• Architect, develop, and enhance scalable UVM-based verification environments and reusable verification IP.
• Define verification strategies and test plans from specification review through product release.
• Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
• Drive functional coverage closure and verification signoff activities.
• Debug challenging RTL, protocol, and system-level issues while improving verification efficiency and automation.
• Partner closely with architecture, RTL, firmware, and systems teams to identify issues early and ensure robust product quality.

Skills

SystemVerilog

UVM

PCIe

CXL

DDR interfaces

Ethernet

Constrained-random verification

Coverage-driven verification

Debug RTL/protocol

VCS/ModelSim

Education

BSEE/BSEE or MS in EE

Tools

VCS

ModelSim

Job description

Synopsys Inc. is seeking an experienced ASIC Verification Engineer to own verification of Interface IP.

You will design, develop, and maintain scalable UVM-based environments for PCIe, CXL, DDR, and Ethernet, collaborating with architects, RTL, and firmware teams to ensure high-quality, robust silicon products. The role emphasizes coverage-driven verification, debugging, and early issue detection, contributing to the reliability and performance of AI accelerators, data centers, and networking