Mid-Senior ASIC RTL Verification Engineer (DDR/Memory IP)

Infobahn Softworld Inc; Santa Clara (CA); Hybrid; USD 120,000 - 150,000; Full time

Job summary

A technology company in Santa Clara is seeking an adaptive Design Verification Engineer to improve ASIC design verification processes. The ideal candidate has over 10 years of experience and expertise in C/C++, Verilog, and modern verification libraries. Responsibilities include developing tests for functional verification and collaborating with cross-functional teams. This position is contract-based and encourages a supportive workplace.

Qualifications

• 10+ years of ASIC design verification experience.
• Understanding of Design for Test methodologies and DFT verification experience is a plus.

Responsibilities

• Develop/Maintain tests for functional verification.
• Build the directed and random verification tests, debug test failures, and work with RTL and firmware engineers.

Skills

C/C++

Verilog

System Verilog

Python

Perl

TCL

Debugging firmware and RTL code

Education

Bachelor’s or master’s degree in computer engineering/Electrical Engineering

Job description

A technology company in Santa Clara is seeking an adaptive Design Verification Engineer to improve ASIC design verification processes. The ideal candidate has over 10 years of experience and expertise in C/C++, Verilog, and modern verification libraries. Responsibilities include developing tests for functional verification and collaborating with cross-functional teams. This position is contract-based and encourages a supportive workplace.