Remote DDR Design Verification Lead (10+ yrs)

RAPS Consulting Inc; Edison (NJ); Remote; USD 100,000 - 130,000; Full time

Job summary

A leading staffing company is seeking a Design Verification Engineer with over 10 years of experience in ASIC/IP/SoC verification. The role involves defining verification strategies for DDR interfaces and developing testbenches in SystemVerilog. This position offers full-time employment and is remote within the United States. Candidates should have strong technical skills and experience with DDR protocols and simulation tools.

Qualifications

• 10+ years of hands-on experience in ASIC/IP/SoC verification.
• Strong expertise in SystemVerilog, UVM, and functional coverage methodology.
• In-depth understanding of DDR protocols.

Responsibilities

• Define and implement verification strategies and test plans for DDR memory interfaces.
• Develop UVM/SystemVerilog-based testbenches.
• Collaborate with architecture, RTL, and system teams.

Skills

ASIC/IP/SoC verification

SystemVerilog

UVM

DDR3/DDR4/DDR5/LPDDR protocols

Simulation and debug tools

Python scripting

Debugging

Tools

Synopsys VCS

Cadence Xcelium

QuestaSim

Job description

A leading staffing company is seeking a Design Verification Engineer with over 10 years of experience in ASIC/IP/SoC verification. The role involves defining verification strategies for DDR interfaces and developing testbenches in SystemVerilog. This position offers full-time employment and is remote within the United States. Candidates should have strong technical skills and experience with DDR protocols and simulation tools.