Interface IP Verification Engineer (PCIe/CXL/DDR/Ethernet)

Synopsys, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Verification Engineer to tackle complex protocol challenges and deliver world-class Interface IP solutions.

You will work on PCIe, CXL, DDR, and Ethernet technologies that underpin AI accelerators, data centers, and SoCs, collaborating with architects, RTL, firmware, and systems teams to ensure high quality outcomes. The role emphasizes developing scalable verification environments, driving coverage, and mentoring engineers to advance verification

Qualifications

• 8–10+ years in ASIC/SoC verification or equivalent industry experience.
• Strong SystemVerilog and UVM expertise with scalable verification.
• Proficient in PCIe, CXL, DDR, and Ethernet verification.
• Experience developing constrained-random and coverage-driven environments.

Responsibilities

• Own verification of Interface IP solutions such as PCIe, CXL, DDR, and Ethernet.
• Architect, develop, and enhance scalable UVM-based verification environments and reusable VI.
• Define verification strategies and test plans from specs through release.
• Develop constrained-random, coverage-driven verification solutions using SystemVerilog and UVM.
• Drive coverage closure and verification signoff activities.
• Debug RTL, protocol, and system-level issues while improving efficiency.
• Mentor engineers and influence verification methodology across teams.

Skills

SystemVerilog

UVM

PCIe

CXL

DDR interfaces

Ethernet

Debugging

Mentoring

Education

BSEE or MS in Electrical Engineering

Tools

VCS

ModelSim

Job description

Synopsys, Inc. is seeking an experienced ASIC Verification Engineer to tackle complex protocol challenges and deliver world-class Interface IP solutions.

You will work on PCIe, CXL, DDR, and Ethernet technologies that underpin AI accelerators, data centers, and SoCs, collaborating with architects, RTL, firmware, and systems teams to ensure high quality outcomes. The role emphasizes developing scalable verification environments, driving coverage, and mentoring engineers to advance verification