Lead ASIC Verification Engineer - DDR & IP Architectures

AMD; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

AMD is seeking an ASIC Design Verification Engineer in Austin, Texas, to develop cutting-edge verification methodologies for DDR technologies. The role involves working in a collaborative environment, developing verification architecture, and ensuring the quality of complex IP blocks.

The ideal candidate will have a BS/MS in Engineering or Computer Science, strong skills in SystemVerilog and UVM, and experience in ASIC verification. AMD offers competitive benefits and values diverse perspectives in its workforce.

Qualifications

• Experience in ASIC verification.
• Strong understanding of digital design and computer architecture.
• Ability to debug SystemVerilog RTL code using simulation tools.

Responsibilities

• Collaborate with IP architects to develop verification architecture.
• Participate in verification of complex IP blocks.
• Develop and maintain scripts and tools.

Skills

Analytical thinking

Problem-solving skills

Teamwork

Communication skills

Attention to detail

Education

BS/MS degree in Engineering or Computer Science

Tools

SystemVerilog

UVM

Verilog

C/C++

Linux

Windows

Job description

AMD is seeking an ASIC Design Verification Engineer in Austin, Texas, to develop cutting-edge verification methodologies for DDR technologies. The role involves working in a collaborative environment, developing verification architecture, and ensuring the quality of complex IP blocks.

The ideal candidate will have a BS/MS in Engineering or Computer Science, strong skills in SystemVerilog and UVM, and experience in ASIC verification. AMD offers competitive benefits and values diverse perspectives in its workforce.