AI Accelerator Verification Lead

Velaura; Santa Clara (CA); On-site; USD 200,000 - 350,000; Full time

Job summary

Velaura is seeking a Design Verification Engineer to help verify its next‑generation Physical AI SoC focused on AI acceleration units. You will verify hardware correctness, performance, and numerical behavior from RTL blocks to full systems, collaborating with architects, RTL engineers, software teams and system teams.

The role emphasizes creating test and coverage plans, developing reference models for GEMM/GEMV, and validating data flow, precision, and performance per watt under representative

Qualifications

• 8 or more years verifying high performance compute or complex digital designs.
• High level understanding of LLMs including transformer structure and inference data flow.
• Knowledge of GEMM and GEMV operations and how they map onto hardware.
• Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
• Experience building or using reference models in C, C++ or Python.
• Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
• Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
• BS or higher in Computer Engineering, Electrical Engineering or Computer Science.

Responsibilities

• Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
• Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
• Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
• Develop reference models for GEMM and GEMV operations and compare hardware results against them.
• Verify accelerator data flow including operand staging, tiling, accumulation and result writeback.
• Verify precision, rounding and quantization behavior against the architecture specification.
• Verify throughput, latency, utilization and performance per watt against aggressive targets under representative LLM and vision workloads.
• Execute regressions through design and environment bring up, track progress using bug and coverage metrics, and support emulation and pre silicon bring up with the compiler and runtime teams.

Skills

High performance compute verification

LLM/inference data flow understanding

Numerical formats and precision trade‑

Education

BS or higher in Computer Engineering, Electrical Engineering or Computer Science

Tools

SystemVerilog

UVM

C

C++

Python

Assertions & coverage

Job description

Velaura is seeking a Design Verification Engineer to help verify its next‑generation Physical AI SoC focused on AI acceleration units. You will verify hardware correctness, performance, and numerical behavior from RTL blocks to full systems, collaborating with architects, RTL engineers, software teams and system teams.

The role emphasizes creating test and coverage plans, developing reference models for GEMM/GEMV, and validating data flow, precision, and performance per watt under representative