Senior Physical AI SoC Verification Engineer — Equity

Velaura AI, Inc.; Santa Clara (CA); Hybrid; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking a Design Verification Engineer to verify a next-generation Physical AI SoC. You will collaborate with architects, RTL and software teams to ensure correctness, performance, and safety across RTL blocks and full HW/SW systems under real workloads.

We welcome engineers at all levels who enjoy tackling complex problems, corner cases, and system-level verification, from early architecture through post-silicon phases, with exposure to AI-enabled verification workflows.

Qualifications

• 10+ years of experience verifying complex digital systems.
• Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.
• Experience with CDC issues, clocking and reset verification.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Experience with emulation, FPGA prototyping, or pre-silicon validation environments.

Responsibilities

• Develop and execute verification strategies for key portions of the Velaura SoC.
• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

SystemVerilog

UVM

C/C++

Formal verification

Emulation

FPGA prototyping

SoC architecture

Debugging complex systems

Tools

Emulation platforms

Job description

Velaura AI, Inc. is seeking a Design Verification Engineer to verify a next-generation Physical AI SoC. You will collaborate with architects, RTL and software teams to ensure correctness, performance, and safety across RTL blocks and full HW/SW systems under real workloads.

We welcome engineers at all levels who enjoy tackling complex problems, corner cases, and system-level verification, from early architecture through post-silicon phases, with exposure to AI-enabled verification workflows.