Senior CPU Physical Design Engineer (PPA & Signoff)

RosaicLabs Inc; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical benefits (Health)

Dental and Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc in Austin, TX seeks an experienced CPU Physical Design Engineer to drive macro-level and gate-level design decisions for high‑performance ASIC blocks. The role emphasizes timing, power, and area optimization across complex CPU datapaths and memory structures.

You will collaborate with RTL, DFT, verification, and packaging teams to ensure successful PPA outcomes, and lead physical design flows and signoff procedures to meet aggressive silicon targets.

Qualifications

• Master's degree required or equivalent in E.E. or related field.
• 5+ years of industry experience in CPU/high‑performance ASIC physical design.
• Strong understanding of CPU microarchitecture, pipelines, caches, branch prediction, interconnect.
• Gate-level design experience including standard-cell logic and clock/reset architecture.
• Proficient in using EDA tools for synthesis, P&R, and signoff.

Responsibilities

• Analyze CPU microarchitecture to guide timing, power, and area tradeoffs.
• Develop and own gate-level design for CPU blocks and clock-domain architectures.
• Perform transistor-level design for critical paths, register files, datapaths, memory arrays.
• Drive synthesis, floorplanning, CTS, placement, and routing to closure.
• Own STA, signal integrity, IR drop/electromigration analysis, and signoff.
• Debug and close timing, power, and DRC/LVS violations across corners and modes.

Skills

Scripting (Tcl/Python/Perl)

Education

Master's degree in Electrical/Computer Engineering

Tools

EDA tools for synthesis, P&R, signoff

Job description

RosaicLabs Inc in Austin, TX seeks an experienced CPU Physical Design Engineer to drive macro-level and gate-level design decisions for high‑performance ASIC blocks. The role emphasizes timing, power, and area optimization across complex CPU datapaths and memory structures.

You will collaborate with RTL, DFT, verification, and packaging teams to ensure successful PPA outcomes, and lead physical design flows and signoff procedures to meet aggressive silicon targets.