Senior CPU Physical Design Engineer - PPA Expert

RosaicLabs; Santa Clara (CA); Vor Ort; USD 125.000 - 250.000; Vollzeit

Benefits dieser Stelle

Medical benefits

Dental

Vision

Life & AD&D

401(k)

Zusammenfassung

RosaicLabs is seeking an experienced design engineer to lead physical design of CPU blocks in a high-performance ASIC. You will analyze microarchitecture, perform gate- and transistor-level design, and drive CTS, P&R, and power integrity.

You will own STA, SI, and signoff checks while working with RTL, DFT, verification, and packaging teams to optimize power, performance, and area. A Master’s degree and 5+ years of ASIC experience are required.

Qualifikationen

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of industry experience in CPU or high-performance ASIC physical design.
• Strong understanding of CPU microarchitecture, pipelines, OOO, caches, branch prediction.
• Gate-level design experience with standard-cell logic and clock/reset architecture.
• Transistor-level/custom circuit design for high-speed and low-power structures.
• Proven track record driving synthesis and place-and-route to timing, power, and area closure.
• Solid grasp of STA, signal integrity, and physical verification (DRC/LVS).
• Proficient with industry-standard EDA tools for synthesis, P&R, and signoff.
• Scripting proficiency in Tcl, Perl, or Python for flow automation.

Aufgaben

• Analyze CPU microarchitecture to guide timing, power, and area tradeoffs.
• Develop gate-level design for CPU blocks and clock-domain architecture.
• Perform transistor-level design for critical paths and memories.
• Drive synthesis, floorplanning, CTS, and routing to closure.
• Own STA, SI, IR drop, and electrical signoff; debug timing/power issues.
• Collaborate with RTL, DFT, verification, and package teams to optimize PPA.
• Improve physical design flows, scripts, and methodologies for QoR.

Kenntnisse

CPU microarchitecture

Gate-level design

5+ years experience

P&R closure

STA

Fabrication verification

Scripting (Tcl/Perl/Python)

Ausbildung

Master's degree in Electrical or Computer Engineering

Tools

EDA tools

Synthesis tools

CTS/CTS

Jobbeschreibung

RosaicLabs is seeking an experienced design engineer to lead physical design of CPU blocks in a high-performance ASIC. You will analyze microarchitecture, perform gate- and transistor-level design, and drive CTS, P&R, and power integrity.

You will own STA, SI, and signoff checks while working with RTL, DFT, verification, and packaging teams to optimize power, performance, and area. A Master’s degree and 5+ years of ASIC experience are required.