Senior CPU Physical Design Engineer – On-Site Austin

Intel Corporation; Austin (TX); Presencial; USD 142.000 - 232.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock bonuses

Health benefits

Retirement plan

Vacation

Descripción de la vacante

Intel Corporation in Texas, Austin, is seeking an experienced CPU physical design engineer to drive RTL-to-GDS implementation for high-performance cores. You will lead the full design flow, optimize for power, frequency and area, and collaborate with logic, circuit, architecture and EDA teams to push boundary technology.

You'll bring 6+ years of relevant experience (or an MS with 4+ years) in Synthesis, timing analysis, and physical verification, and be proficient with Synopsys/Cadence tools and

Formación

• Bachelor's or higher in Computer or Electrical Engineering with relevant work experience.
• Minimum 6+ years of relevant hardware design experience or MS with 4+ years.
• Completion of Tape Out on advanced technologies.
• Experience with IC design tools (Synopsys/Cadence) including synthesis, place and route, STA and design closure.
• PV convergence, timing analysis, power integrity, and signoff.
• Scripting with TCL as part of design automation.

Responsabilidades

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, STA, power/clock distribution, reliability, and power/noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, EDA checks, and optimization recommendations.
• Possesses CPU-specific expertise in physical design, clock design, timing closure, and DFT considerations; collaborates with logic, circuit, architecture and design automation teams.
• Works with industry EDA vendors to enhance tool capabilities for highspeed, low power CPU design; strives to improve physical design methodologies and flow automation.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area; participates in timing constraints and chip-level timing balance.

Conocimientos

Synthesis of digital logic blocks

Clock distribution and timing closure

RTL to GDS workflow understanding

Scripting with TCL

Power/area optimization

Educación

Bachelor's degree in Computer Engineering or Electrical Engineering

Master's degree in Computer Engineering or Electrical Engineering

Herramientas

Synopsys

Cadence

PV convergence

Electrical Rule Check (ERC) and DRC/LVS

TCL scripting

Descripción del empleo

Intel Corporation in Texas, Austin, is seeking an experienced CPU physical design engineer to drive RTL-to-GDS implementation for high-performance cores. You will lead the full design flow, optimize for power, frequency and area, and collaborate with logic, circuit, architecture and EDA teams to push boundary technology.

You'll bring 6+ years of relevant experience (or an MS with 4+ years) in Synthesis, timing analysis, and physical verification, and be proficient with Synopsys/Cadence tools and