CPU Physical Design Engineer - Full Time

RosaicLabs; Santa Clara (CA); On-site; USD 125,000 - 250,000; Full time

Benefits offered by this job

Medical benefits

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs is seeking an experienced design engineer to lead physical design of CPU blocks in a high-performance ASIC. You will analyze microarchitecture, perform gate- and transistor-level design, and drive CTS, P&R, and power integrity.

You will own STA, SI, and signoff checks while working with RTL, DFT, verification, and packaging teams to optimize power, performance, and area. A Master’s degree and 5+ years of ASIC experience are required.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of industry experience in CPU or high-performance ASIC physical design.
• Strong understanding of CPU microarchitecture, pipelines, OOO, caches, branch prediction.
• Gate-level design experience with standard-cell logic and clock/reset architecture.
• Transistor-level/custom circuit design for high-speed and low-power structures.
• Proven track record driving synthesis and place-and-route to timing, power, and area closure.
• Solid grasp of STA, signal integrity, and physical verification (DRC/LVS).
• Proficient with industry-standard EDA tools for synthesis, P&R, and signoff.
• Scripting proficiency in Tcl, Perl, or Python for flow automation.

Responsibilities

• Analyze CPU microarchitecture to guide timing, power, and area tradeoffs.
• Develop gate-level design for CPU blocks and clock-domain architecture.
• Perform transistor-level design for critical paths and memories.
• Drive synthesis, floorplanning, CTS, and routing to closure.
• Own STA, SI, IR drop, and electrical signoff; debug timing/power issues.
• Collaborate with RTL, DFT, verification, and package teams to optimize PPA.
• Improve physical design flows, scripts, and methodologies for QoR.

Skills

CPU microarchitecture

Gate-level design

5+ years experience

P&R closure

STA

Fabrication verification

Scripting (Tcl/Perl/Python)

Education

Master's degree in Electrical or Computer Engineering

Tools

EDA tools

Synthesis tools

CTS/CTS

Job description

What you’ll do

• Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area

• Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture

• Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)

• Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure

• Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff

• Debug and close timing, power, and DRC/LVS violations across corners and modes

• Collaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)

• Develop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time

• Participate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps

What we’re looking for

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field

• 5+ years of industry experience in CPU or high-performance ASIC physical design

• Strong understanding of CPU microarchitecture: pipelines, out-of-order execution, caches, branch prediction, and interconnect

• Hands-on experience with gate-level design, including standard-cell logic design and clock/reset architecture

• Working knowledge of transistor-level/custom circuit design for high-speed and low-power structures

• Proven track record driving synthesis and place-and-route (P&R) to timing, power, and area closure on complex blocks

• Solid grasp of static timing analysis (STA), signal integrity, and physical verification (DRC/LVS)

• Proficiency with industry-standard EDA tools for synthesis, P&R, and signoff (see Tools & Technologies)

• Scripting proficiency in Tcl, Perl, or Python for flow automation

• Strong analytical and debugging skills, with the ability to work through cross-corner, cross-mode PPA tradeoffs

$125,000 - $250,000 a year

Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)