CPU Physical Design (RTL to GDS) Physical Design Austin / Santa Clara · Hybrid

NUVACORE, Inc.; Texas; Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

NUVACORE, Inc. is seeking a CPU Physical Design Engineer to drive end-to-end design closure from RTL to GDS/tape-out while optimizing power, performance, and area. You will coordinate with CAD, RTL/μ-arch, and partner teams to ensure timely design cycle progress and PPAs.

The role requires strong experience in PD signoff and DFT timing, plus excellent collaboration and communication abilities to influence tools and methodologies across the team.

Qualifications

• Hold a BS or MS degree in Electrical Engineering or related field with 5+ years (IC) or 12+ years (Lead) CPU PD experience.
• Proficient in industry-standard EDA tools and CPU design workflows.
• Track record of delivering production-level designs through tape-out.
• Experience in PPA optimization across CPU units and design blocks.
• Strong understanding of end-to-end physical design closure including signoff domains and DFT timing constraints.
• Excellent communication and cross-team collaboration skills.

Responsabilités

• Evaluate RTL and micro-architecture designs, providing feasibility assessments and actionable feedback.
• Drive end-to-end design closure from RTL to GDS/tape-out meeting PPAs (Power, Performance, Area & Schedule).
• Coordinate with CAD, RTL/μ-arch, and partner teams to ensure seamless execution through the design cycle.
• Lead and influence Tools, Flows, and Methodology (TFM) adoption to boost design efficiency and establish best practices.

Connaissances

CPU PD

PPA optimization

End-to-end PD

Team collaboration

Python/TCL/Perl

EDA tools

Communication

Formation

BS or MS in Electrical Engineering

Outils

EDA tools suite

Python

Perl

TCL

Agentic AI tools

Description du poste

Nuvacore is building ground-up high performance, low power CPU for next generation compute workloads. As a member of CPU - specific custom circuit design team, you will enable the design to achieve the target PPA Specifications for the product.

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following :

Responsible for evaluating RTL and micro-Architecture designs, providing feasibility assessments and actionable feedback.

Responsible for driving end-to-end design closure from RTL to GDS/Tape-out, ensuring target PPAS (Power, Performance, Area & Schedule) commitments are met.

Responsible for coordinating and aligning with CAD, RTL/µ-arch, and other partner teams to ensure seamless execution throughout the design cycle.

Responsible for leading and influencing the definition and adoption of Tools, Flows, and Methodology (TFM) to drive design efficiency and establish team-wide best practices

MUST TO HAVE

Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.

Proficient in industry-standard EDA tools with experience applied to CPU design workflows.

Demonstrated track record of successfully delivering production-level designs through tape-out.

Proven experience in PPA optimization across CPU units and design blocks.

Deep understanding of end-to-end physical design closure, spanning all signoff domains

Well-versed in timing constraints for both Functional and DFT (Design for Test) modes.

Strong communication and collaboration skills

REQUIREMENTS NICE TO HAVE

Possess substantial years of experience in CPU unit-level implementation

Demonstrate ability to translate architectural intent into physical design decisions.

Bring proven experience in PPA-focused design execution for CPUs, including hands-on tool optimization to achieve power, performance, and area targets.

Hold a deep understanding of Physical Design (PD) signoff checks and methodologies, including FEV, VCLP, EM/IR, STA/EXT, and associated closure flows.

Exhibit thoroughness and precision in ECO (Engineering Change Order) flows.

Proficient in Python, Perl, or TCL to enhance design productivity and flow efficiency

Experience in using Agentic AI tools for productivity and automation.