Senior CPU Physical Design Engineer - PPA & Timing Lead

Qualcomm; San Diego (CA); On-site; USD 211,900 - 317,900; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Comprehensive benefits package

Job summary

Qualcomm is seeking a CPU Physical Design expert to drive the next generation of computing in San Diego. In this key role, you will own critical CPU implementation tasks, optimizing performance and efficiency while collaborating with teams on forward-thinking design strategies. The position demands over 10 years of ASIC/SoC experience and expertise with RTL-to-GDSII processes.

Enjoy working on cutting-edge technology with opportunities for career advancement and competitive compensation, including bonuses and RSU grants.

Qualifications

• 10+ years of experience in ASIC/SoC Physical Design.
• Strong experience with RTL-to-GDSII implementation.
• Experience in timing closure and power optimization.

Responsibilities

• Own critical portions of CPU implementation from RTL to GDS.
• Drive optimization for high-frequency, complex CPU subsystems.
• Partner with teams to co-optimize design for physical implementation.

Skills

ASIC/SoC Physical Design

RTL-to-GDSII implementation

Timing closure

Power optimization

Scripting skills (TCL, Python)

Education

Bachelor’s in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Job description

Qualcomm is seeking a CPU Physical Design expert to drive the next generation of computing in San Diego. In this key role, you will own critical CPU implementation tasks, optimizing performance and efficiency while collaborating with teams on forward-thinking design strategies. The position demands over 10 years of ASIC/SoC experience and expertise with RTL-to-GDSII processes.

Enjoy working on cutting-edge technology with opportunities for career advancement and competitive compensation, including bonuses and RSU grants.