Lead AI Accelerator Physical Design Engineer

RosaicLabs Inc; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

RosiacLabs Inc. in Austin, TX is seeking a senior hardware physical design engineer to own and drive the full flow from synthesis to routing for accelerator blocks and top-level designs.

You will develop floorplans for compute tiles and large SRAMs, optimize for timing, power, and area, and work with RTL, DFT, and verification teams to ensure physical implementability. A strong background in low-power design and SLT is essential.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of industry experience in high performance, low power physical design.
• Hands-on experience taking complex digital designs through synthesis, place-and-route, and signoff at advanced process nodes.
• Strong understanding of timing closure, clocking, and static timing analysis, including OCV and multi-corner multi-mode analysis.
• Experience with power integrity: power grid design, IR drop, and electromigration.
• Experience with physical verification (DRC/LVS) and fixing violations.
• Familiarity with accelerator or compute-array architectures, such as systolic arrays, SIMD/vector engines, and large on-chip memories.
• Proficiency with industry-standard EDA tools (see Tools & Technologies).
• Scripting skills in Tcl, Python, or Perl for flow automation.
• Strong debugging skills and the ability to work with RTL, architecture, and DFT teams.

Responsibilities

• Own physical implementation of accelerator blocks and top level: synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing.
• Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement, balancing congestion, wire length, and utilization.
• Close timing, power, and area (PPA) targets, including optimization of datapath-heavy and high-fanout structures.
• Manage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation.
• Implement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains.
• Run static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes.
• Partition and implement hierarchical designs, including budgeting and integration of replicated blocks.
• Work with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability.
• Develop and maintain automation for flows, regressions, and QoR tracking.
• Support silicon bring-up and correlate post-silicon results with pre-silicon predictions.

Skills

5+ years experience in high perf, low‑

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

EDA tools

Job description

RosiacLabs Inc. in Austin, TX is seeking a senior hardware physical design engineer to own and drive the full flow from synthesis to routing for accelerator blocks and top-level designs.

You will develop floorplans for compute tiles and large SRAMs, optimize for timing, power, and area, and work with RTL, DFT, and verification teams to ensure physical implementability. A strong background in low-power design and SLT is essential.