Senior CPU Physical Design Engineer

RosaicLabs Inc; Santa Clara (CA); Presencial; USD 180 000 - 240 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical (including HSA)

Dental

Vision

Life & AD&D

401(k)

Resumo da oferta

RosaicLabs Inc in Santa Clara, CA is seeking a senior IC design engineer to lead CPU block design and physical implementation. You will analyze microarchitectures, own gate-level design, and drive CTS, P&R, and signoff across complex blocks. Collaboration with RTL, verification, and packaging teams is essential.

The role emphasizes heavy involvement in timing, power, and area closure, plus debug of DRC/LVS across corners. A strong background in high-speed ASIC design and SPS flows is required.

Qualificações

• Master's degree or higher in Electrical/Computer Engineering or related field.
• Hands-on experience in CPU/high-performance ASIC physical design.
• Strong understanding of pipelines, caches, branch prediction, and interconnects.

Responsabilidades

• Analyze CPU microarchitecture to guide timing/power/area tradeoffs.
• Develop and own gate-level design for CPU blocks and clock-domain/reset architecture.
• Perform transistor-level design for critical paths and memory structures.
• Drive synthesis, floorplanning, CTS, placement, routing to closure.
• Own STA, signal integrity, IR drop, electromigration, and signoff.
• Debug and close timing, power, and DRC/LVS violations across corners.
• Collaborate with RTL, DFT, verification, and package teams to optimize PPA.
• Develop and improve physical design flows, scripts, and methodologies.

Conhecimentos

CPU microarchitecture understanding

Gate-level design experience

Scripting in Tcl/Perl/Python

PPA tradeoffs and debugging

Analytical thinking

Formação académica

Master's degree in Electrical or Computer Engineering

Ferramentas

EDA tools for synthesis/PR/signoff

Descrição da oferta de emprego

RosaicLabs Inc in Santa Clara, CA is seeking a senior IC design engineer to lead CPU block design and physical implementation. You will analyze microarchitectures, own gate-level design, and drive CTS, P&R, and signoff across complex blocks. Collaboration with RTL, verification, and packaging teams is essential.

The role emphasizes heavy involvement in timing, power, and area closure, plus debug of DRC/LVS across corners. A strong background in high-speed ASIC design and SPS flows is required.