Senior CPU Microarchitecture & RTL Design Engineer

AheadComputing, Inc.; Portland (OR); On-site; USD 120,000 - 190,000; Full time

Job summary

AheadComputing, Inc. is seeking a Senior CPU Design Engineer to design and implement high-performance execution units, optimizing for power, performance, and area (PPA). You will shape microarchitecture, develop RTL, and validate designs across cross-functional teams.

You will collaborate with verification and physical design teams to ensure timing, area and reliability targets are met, and you will prototype and validate core and subsystem RTL across simulations and silicon.

Qualifications

• Bachelor's degree with 4+ years of related experience, or higher degree with fewer years.
• Strong understanding of microprocessor architecture and microarchitecture.
• Experience with SystemVerilog RTL development and front-end tools.
• Proficient in C/C++ and Python; strong analytical skills.

Responsibilities

• Define, develop, and refine microarchitecture specifications for complex CPU subsystems.
• Design and implement RTL to meet target power, performance, area, and timing goals.
• Collaborate with verification to establish validation strategies for new designs.
• Support test bench development and assist validation engineers in testing and debugging RTL.
• Work with physical design teams to meet timing, area, and power requirements.

Skills

Microprocessor architecture

PPA optimization

Problem solving

Cross‑functional collaboration

RTL debugging

Education

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or related field

Master's degree in Electrical/Computer Engineering, Computer Science, or related field

PhD in a related field

Tools

SystemVerilog RTL development

Verilog simulators

Logic synthesis

Place-and-route tools

C/C++

Python

Job description

AheadComputing, Inc. is seeking a Senior CPU Design Engineer to design and implement high-performance execution units, optimizing for power, performance, and area (PPA). You will shape microarchitecture, develop RTL, and validate designs across cross-functional teams.

You will collaborate with verification and physical design teams to ensure timing, area and reliability targets are met, and you will prototype and validate core and subsystem RTL across simulations and silicon.