Senior ASIC Physical Design Lead - Timing & PPA

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking a hands-on Senior Physical Design Engineer to lead and contribute to advanced-node implementation of ASIC/SoC blocks.

You will drive timing closure, ECOs, and PPA optimization across block, subsystem, and chip-level designs, collaborating with architecture, RTL, CAD, and verification teams to deliver high-quality silicon. You will mentor engineers, evolve design methodologies, and advance automation.

Qualifications

• Experience with ASIC physical design and timing closure.
• Experience across block, subsystem, and chip-level design environments.
• Strong knowledge of STA, clock-tree synthesis, signoff, and ECO methodologies.

Responsibilities

• Lead physical design activities across block, subsystem, and chip-level implementations.
• Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
• Develop and enhance physical design methodologies, design flows, and automation solutions.
• Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
• Define and execute ECO strategies throughout implementation and signoff.
• Support formal verification, physical verification, and tapeout preparation activities.
• Analyze design data and trends to improve design quality, predictability, and efficiency.
• Collaborate with cross-functional teams to achieve silicon delivery.
• Contribute to AI-assisted and machine learning-driven design optimization initiatives.
• Troubleshoot complex implementation challenges and develop scalable solutions.

Skills

ASIC physical design

Timing closure

Scripting (TCL/Python)

Automation

Education

Bachelor's or Master's in ECE/CE/CS

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

PrimeTime PX

PrimeShield

RedHawk

Formality

Conformal

Job description

Advanced Micro Devices, Inc. (AMD) is seeking a hands-on Senior Physical Design Engineer to lead and contribute to advanced-node implementation of ASIC/SoC blocks.

You will drive timing closure, ECOs, and PPA optimization across block, subsystem, and chip-level designs, collaborating with architecture, RTL, CAD, and verification teams to deliver high-quality silicon. You will mentor engineers, evolve design methodologies, and advance automation.